This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
As is known in the art, large mainframe computer systems require large capacity data storage systems. These large main frame computer systems generally includes data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the main frame computer system are coupled together through an interface. The interface includes CPU, or xe2x80x9cfront endxe2x80x9d, controllers and xe2x80x9cback endxe2x80x9d disk controllers. The interface operates the controllers in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. No. 5,206,939, entitled xe2x80x9cSystem and Method for Disk Mapping and Data Retrievalxe2x80x9d, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. patent, the interface may also include, in addition to the CPU controllers and disk controllers, addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the main frame computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the main frame computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a pair of buses. One set of the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set of the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both buses. Each one of the buses provides data, address and control information.
Thus, the use of two buses provides a degree of redundancy to protect against a total system failure in the event that the controllers, or disk drives connected to one bus fail.
In accordance with the present invention, a data storage system is provided. The data storage system includes a plurality of control/data buses. A memory section is coupled to the plurality of control/data buses. memory section includes a plurality of memory regions and a plurality of control logic sections arranged in a matrix of rows and columns. the control logic sections in each one of the rows thereof is connected to a corresponding one of the plurality of memory regions. The control logic sections in each one of the columns thereof is connected to a corresponding one of the control/data buses.
In accordance with another feature of the invention, each one of the rows of control logic sections are interconnected through an arbitration bus.
In accordance with another feature of the invention, each one of the control logic sections is coupled between a corresponding one of the control/data buses and the memory region. Each one of such control logic sections includes a control logic for controlling transfer of data between the memory and the one of the plurality of control/data buses coupled to said one of the logic sections. The control logic is adapted to produce a control/data bus request for the one of the control/data buses coupled thereto and is adapted to effect the transfer in response to a control/data bus grant fed to the control logic. Each one of the control logic sections also includes a bus arbitration section coupled to the arbitration bus. Each one of the bus arbitration sections is adapted to: (1) receive a control/data bus request from the control logic in such one of the control logic sections and from the other control logic sections coupled to such arbitration bus; (2) grant access to the control/data bus to one of the control logic sections in accordance with the control/data bus requests coupled to the bus arbitration section; (3) receive control/data bus grants from the other control logic sections coupled to such arbitration bus; and (4) distribute the control/data bus request produced by the control logic in said control logic section to the other control logic sections coupled to the arbitration bus.
In accordance with another feature of the invention, each one of the bus arbitration sections includes a majority gate fed by the control/data bus grants received from the other control logic sections for producing an internal control/data bus grant when a majority of the control logic sections indicate that the said one of the bus arbitration sections has been granted the control/data bus.
In accordance with another feature of the invention, each one of the bus arbitration sections includes an internal arbitrator response to control/data bus request from the plurality of control logic sections and provides a control/data bus grant to one of the plurality of control logic sections selectively in accordance with a pre-determined criteria.
In accordance with another feature of the invention, each one of the bus arbitration sections includes an internal arbitrator response to control/data bus request from the plurality of control logic sections and wherein each one of the plurality of control logic sections provides a control/data bus grant to one of the plurality of control logic sections selectively in accordance with a common predetermined criteria.